1. Field of the Invention
The present invention relates to a voltage regulator and a method of voltage regulation.
2. Description of Prior Art
FIG. 1 illustrates a prior art voltage regulator 8 used on, for example, FLASH memory designs to generate regulated voltages below three volts for a variable load 24 from a five volt power supply. As shown in FIG. 1, the voltage regulator 8 includes a first N-MOS transistor 10 with a drain connected via a first resister 12 to a high potential voltage source VDD. The source of the first N-MOS transistor 10 is connected by a second resister 14 to a low potential voltage source VSS. The gate of the first N-MOS transistor 10 receives an input voltage, and the substrate of the first N-MOS transistor 10 is biased at the low potential VSS.
The source of a P-MOS transistor 20, included in the voltage regulator 8, is also connected to the high potential voltage source VDD, and the drain of the P-MOS transistor 20 is connected to the source of the first N-MOS transistor 10. As shown in FIG. 1, the drain of the P-MOS transistor 20 serves as the output for the voltage regulator 8. A gate of the P-MOS transistor 20 is connected to the drain of the first N-MOS transistor 10, and the substrate of the P-MOS transistor 20 is biased at the high potential VDD.
FIG. 1 illustrates one possible example of a variable load 24. As shown, the variable load 24 includes a capacitor 16 connected between the output of the voltage regulator 8 and ground. A switch 18 is connected in series with a third resistor 22 between the output of the voltage regulator 8 and ground as well.
During operation, as the switch 18 opens and closes, the load on the output of the voltage regulator 8 changes. However, the voltage regulator 8 compensates for these changes in load, and maintains a substantially constant voltage at the output. As the discussion below will reveal, the voltage maintained at the output depends on the voltage supplied to the input of the voltage regulator 8.
When the load on output of the voltage regulator 8 increases, the voltage at the output of the voltage regulator 8 drops. When the voltage at the output becomes less than the input voltage minus the threshold of the first N-MOS transistor 10, the first N-MOS transistor 10 turns on. As a result, current flows through the first N-MOS transistor 10 and the voltage at the gate of the P-MOS transistor 20 drops sufficiently to turn on the P-MOS transistor 20. With the P-MOS transistor 20 on, the output voltage is pulled high. Specifically, the output voltage reaches the input voltage minus the threshold of the first N-MOS transistor 10. Accordingly, the voltage regulator 8 operates based on the feedback output voltage.
Because the source of the first N-MOS transistor 10 is above the low potential VSS, the threshold of the first N-MOS transistor 10 increases due to the back-gate bias effect, and can be as high as a few volts. In other words, as the output voltage increases so does the threshold of the first N-MOS transistor 10. Therefore, the output voltage can only attain a maximum voltage of about three volts when the high potential VDD is five volts.
FIG. 5 illustrates the output voltage with respect to the input voltage for both the voltage regulator embodiments of the present invention and the conventional art of FIG. 1 assuming the low potential VSS is 0 volts and the high potential VDD is at least 5 volts. Specifically, a first curve 100 in FIG. 5 illustrates the output voltage with respect to the input voltage for the voltage regulator 8 of FIG. 1. As shown, the voltage regulator 8 generates a regulated output voltage ranging from 0 volts to just over 3 volts. When the input voltage is less than the low potential VSS plus the threshold of the first N-MOS transistor 10 (e.g., below about 0.5V as shown in FIG. 5), the output voltage is no longer regulated and floats at about the low potential VSS.